Memory is used for storage of data, program code, and/or other information in many electronic products, such as personal computer systems, embedded processor-based systems, video image processing circuits, portable phones, and the like. Memory cells may be provided in the form of a dedicated memory integrated circuit (IC) or may be embedded (included) within a processor or other IC as on-chip memory. Ferroelectric memory, sometimes referred to as “FRAM” or “FERAM”, is a non-volatile form of memory commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) configurations, in which each memory cell includes one or more access transistors. The cells are typically organized in an array, and are selected by plateline and wordline signals from address decoder circuitry, with the data being read from or written to the cells along bitlines using sense amp circuits.
Continuing design efforts are directed toward increasing memory density in semiconductor products, by decreasing the size of the cells. In constructing ferroelectric memory cells, the plateline and wordline signals, as well as the bitlines, need to be routed to the appropriate terminals of the cell transistor and capacitor. In a 1T-1C cell, the ferroelectric capacitor is connected between a source/drain of the cell transistor and the plateline signal. The other transistor source/drain is connected to a bitline and the transistor gate is connected to the wordline signal. The configuration of the cell components and interconnect routing structures plays a role in reducing the cell size in an array.
One layout architecture for ferroelectric memory arrays is referred to as ‘capacitor under bitline’, in which the bitlines are routed in an interconnect layer above the layer or level at which the ferroelectric capacitor is formed, where the bitlines are coupled with individual cell transistors using conductive bitline structures (e.g., contacts or vias) extending through the capacitor layer. The capacitor under bitline architecture is preferred for many high-density memories, including embedded memories. In many semiconductor devices employing ferroelectric memory arrays, FRAM processing is performed following standard logic front end processing (e.g., after contact formation in an initial interlevel or interlayer dielectric layer) and before back end processing (e.g., prior to fabrication of overlying metal interconnect layers). In the capacitor under bitline configuration, area must be dedicated to routing the bitline connection from the underlying cell transistor source/drain to the interconnect layer at which the bitline routing structures are created. This requires a bitline contact/via structure that passes vertically through the ferroelectric capacitor level. For planar ferroelectric memory cells of small dimensions (e.g., areas below about 0.25 um2), the size of the ferroelectric capacitor begins to control the cell size. Consequently, the goal of reducing ferroelectric memory cell area and increasing FRAM cell density is facilitated by maximizing the ferroelectric capacitor area in the capacitor layer through which the bitline contact passes.
Another goal in the design and fabrication of ferroelectric memories is to provide reliable transfer of the data to and from the memory cells. In a typical FRAM array, sense amp circuits are coupled with the array bitlines for sensing data from selected memory cells during read operations and for applying voltages to the cells in write operations. Data is read from a ferroelectric memory cell capacitor by connecting a reference voltage to a first bit line and connecting the cell ferroelectric capacitor between a complimentary bit line and a plate line signal voltage, and interrogating the cell. There are several techniques to interrogate a FRAM cell. Two common interrogation techniques are ‘on-pulse’ sensing and ‘after-pulse’ sensing. For on-pulse sensing, the plate line voltage is stepped from ground (Vss) to a supply voltage (Vdd). In the after-pulse sensing the plate line voltage is pulsed from Vss to Vdd and then back to Vss. In either case, the application of the voltage to the plate line provides a differential voltage on the bit line pair, which is connected to the sense amp input terminals. The reference voltage is typically supplied at an intermediate voltage between a voltage (V“0”) associated with a capacitor programmed to a binary “0” and that of the capacitor programmed to a binary “1” (V“1”). The resulting differential voltage at the sense amp terminals represents the data stored in the cell, which is buffered and applied to a pair of local IO lines.
The transfer of data between the ferroelectric memory cell, the sense amp circuit, and the local data bit lines is controlled by various access transistors, typically MOS devices, with switching signals being provided by control circuitry in the device. In a typical ferroelectric memory read sequence, two sense amp bit lines are initially pre-charged to ground, and then floated, after which a target ferroelectric memory cell is connected to one of the sense amp bit lines and interrogated. Thereafter, a reference voltage is connected to the remaining sense amp bit line, and a sense amp senses the differential voltage across the bit lines and latches a voltage indicative of whether the target cell was programmed to a binary “0” or to a “1”.
Capacitance along the array bitlines, referred to as the ‘bitline capacitance’, degrades the signal level of the data being transferred to or from the selected cell along the bitline (e.g., reduces the signal to noise ratio (SNR)). The bitline capacitance typically limits the number of array cells that can be associated with a given sense amp for a given sense margin. However, the goal of higher array cell density is facilitated by increasing the number of ferroelectric memory cells coupled with each bitline, thereby reducing the total number of sense amps required. Thus, for reliable sensing of FRAM cell data and for increasing FRAM cell density, it is important to minimize or reduce the capacitance along the bitlines in the array.